The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with a vertical channel transistor and a method for fabricating the same.
Recently, memory devices of 40 nm or less are required to embody highly integrated semiconductor devices. However, it is difficult to scale a planar or a recessed gate transistor used for 8 F2 (F: minimum feature size) or 6 F2 cell architecture under 40 nm. Thus, a dynamic random access memory (DRAM) device having 4 F2 cell architecture is required to increase the integration degree approximately 1.5 to 2 times while keeping scaling degree at the same level. Accordingly, a vertical channel transistor is introduced.
In the vertical channel transistor, a surround-type gate electrode is formed surrounding active pillars which are vertically extended from a substrate. Source and drain regions are respectively formed in upper and lower portions of the pillars around the gate electrode. Thus, its performance is not restricted by a channel length even though dimensions of the transistor decrease.
FIG. 1A is a cross-sectional view illustrating a structure of a typical semiconductor device with a vertical channel transistor. FIG. 1B is a top view of the typical semiconductor device.
Referring to FIG. 1A, a plurality of pillar structures 100 including a body pillar 12, a head pillar 13, a buffer pattern 14, a hard mask pattern 15, and a capping layer 16 are formed over a substrate 11.
A gate insulation layer 17 and a gate electrode 18 are formed to surround an external wall of the body pillar 12. A buried bit line 19 is formed in the substrate 11. An inter-layer insulation layer 20 is buried in a trench 19A for dividing neighboring bit lines 19.
A wordline 21 is formed in a direction crossing the bit line 19 while being connected to the gate electrode 18.
In the typical method described above, a polysilicon layer is used as the gate electrode 18 and a metal layer is used as the wordline 21.
However, since the wordline 21 is not a metal layer spread continuously in the typical method, but a discontinuous metal layer separated by the polysilicon layer (i.e., the gate electrode 18), the total sheet resistance Rs of the wordline increases affecting driving current flowing through the wordline 21.
For instance, referring to FIG. 1B, since the wordline 21 also includes the polysilicon layer between segments of the metal layers, the driving current flowing through the wordline 21 decreases due to sheet resistance Rp of the polysilicon layer, which is greater than the sheet resistance Rm of the metal layer. Thus, it is difficult to embody high-speed operation.